Field of the Invention
The present invention relates to an integrated circuit for facilitating tests.
Description of the Prior Art
In making large-scale circuits design facilitation by hierarchy has been attempted. However, hierarchy of tests cannot always be accomplished because there are cases in which the preparation of test data is a bottleneck. In addition, there are occurring an increasing number of cases in which circuits with larger scale including the already developed chips are being made. In such a case, the test data on the already developed chips cannot be reused although their design data can be reused.
In order to reuse the test data of the already developed chips, it is necessary to come up with a systematic method which enables the hierarchy of tests. Once a hierarchy of tests becomes feasible, then specification of defective portion becomes easy not only because of the facilitation in the preparation of the test data including the reuse of the test data but also of the possibility of realizing a defect analysis by hierarchy.